Vice President of Silicon Engineering

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's or PhD preferred) 10+ years of experience in ASIC development At least 3 years in management or technical leadership roles Proven track record architecting and/or managing complex mixed-signal ASIC projects through production Deep expertise in advanced digital ASIC design methodologies Strong knowledge of analog and mixed-signal design in specialty process technologies Experience managing multi-project portfolios with internal teams and external design partners Demonstrated success taking ASICs from concept through volume production and qualification Strong understanding of ASIC cost drivers, yield optimization, and manufacturing economics

Define and drive the silicon roadmap aligned with product requirements and photonic PIC integration needs Lead architecture and design of multiple ASICs Establish design methodologies, flows, and best practices Interface closely with photonics, systems, and product teams Drive critical technical decisions on architecture, process selection, IP strategy, and design-for-manufacturing Manage end-to-end ASIC development from specification through tape-out, characterization, qualification, and production ramp Build and maintain relationships with foundries, IP vendors, and design service providers Establish project schedules, resource plans, and budgets Implement risk management strategies Drive design reviews, validation plans, and post-silicon debug activities Build, mentor, and manage a high-performing internal silicon engineering team Recruit top talent across digital design, analog/mixed-signal design, physical design, and verification Manage external contractors and design houses Foster a culture of technical excellence, innovation, and cross-functional collaboration Partner with executive leadership to align silicon strategy with business objectives Support customer engagements with technical presentations Contribute to fundraising and investor communications Drive cost optimization and yield improvement initiatives