Senior FPGA Verification Architect

Bachelor’s/Master’s in EE/CE/CS 10+ years in FPGA/ASIC verification (aerospace preferred) Significant experience performing independent technical reviews, audits, or compliance assessments. Deep expertise in System Verilog & UVM, including architecture-level design of UVM environments Strong understanding of DO-254, DAL-A verification, and requirements-based testing In-depth knowledge of UVM mechanics with ability to architect and construct UVM test benches. Experience reviewing verification plans, UVM TB architecture, coverage models, traceability matrices, and test procedures. Ability to review and propose corrections to low-level test bench implementation. Familiar with Questasim and advanced simulation tool constructs/methodologies. Strong communication skills. Self-motivated, proactive, and comfortable with remote collaboration.

Independently evaluate UVM testbench architecture, coding practices, and component implementation. Review verification strategy, test plans, sequences, constraints, and coverage models. Audit UVM processes and workflows for consistency and compliance. Assess coverage closure metrics and report findings. Provide guidance to distributed teams on UVM best practices. Review and assess DO-254 verification artifacts, requirements, and lifecycle documentation. Evaluate test cases/procedures for requirements-based adequacy. Participate in formal reviews as an independent technical reviewer. Audit verification artifacts for DO-254 DAL-A/B objectives. Validate objective evidence and produce review findings and risk assessments. Contribute to simulation, debugging, and testbench enhancements. Review RTL for correctness, coverage, and testability.