Verification Designer

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Requirements:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 3 years of experience in digital verification.
• Proficient in SystemVerilog and/or VHDL.
• Strong understanding of verification methodologies such as UVM and OVM.
• Familiarity with industry-standard simulation tools (e.g., Questa, ModelSim).
• Experience with Assertions and Coverage-driven verification.
• Knowledge of scripting languages such as Perl or Tcl.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork abilities.
• Self-motivated and proactive approach to work.
• Ability to thrive in a fast-paced and deadline-driven environment.
• Familiarity with FPGA verification is a plus.
• Experience with formal verification techniques is a plus.

Responsibilities:

• Develop and execute verification plans to ensure the functionality and performance of electronic designs.
• Design and implement verification test-benches, test cases, and assertions.
• Perform functional and performance verification of complex digital designs.
• Debug and resolve design issues in a timely manner.
• Generate and maintain accurate documentation of verification activities and findings.
• Continuously enhance the verification process and methodologies.