8+ years of experience designing using RTL/Verilog/VHDL on FPGAs. Experience with video systems and specification standards, video algorithms, and high-speed memory and bus interfaces. Created designs using Xilinx or Altera FPGA families and a solid understanding of tool flow. Experience with Verilog, SystemVerilog, VHDL, Xilinx Vivado, Altera Quartus, and/or ModelSim. Strong communication skills, fluent in English, with customer interaction presence. Proven techniques that lead to high quality design. Degree as a B.A.Sc., B.Eng. or equivalent.