Lead ASIC DFT Engineer
New
S
Sapsol Technologies IncSemiconductor
United StatesContractLead
Salary not disclosed
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Job Details
Requirements
- Strong hands-on experience in ASIC DFT with end-to-end ownership.
- Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
- Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
- Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
- Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
- Experience with MBIST implementation and verification.
- Experience with scan architecture and scan chain stitching.
- Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
- Proven post-silicon debug and silicon bring-up experience.
- Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
Responsibilities
- Architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.
- Maintain end-to-end technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, and boundary scan.
- Lead cross-functional debug efforts for silicon issues.
- Drive resolution of critical silicon issues through post-silicon validation and bring-up.
- Evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
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