Lead ASIC DFT Engineer
S
Sapsol Technologies IncSemiconductors
United StatesContractLead
Salary not disclosed
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Job Details
- Experience
- 10+ years
- Required Skills
- Python
Requirements
- 10+ years of hands-on experience in ASIC Design-for-Test (DFT).
- Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, and boundary scan.
- Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
- Proficiency in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
- Experience with MBIST implementation, verification, and SMS.
- Solid understanding of PLLs, RTL design, synthesis, LEC, and physical design.
- Proven post-silicon debug and silicon bring-up experience.
- Experience with large SoC designs and hierarchical DFT flows.
- Strong scripting skills in TCL, PERL, or Python for automation and debug.
Responsibilities
- Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
- Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows.
- Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up.
- Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure.
- Develop and validate DFT constraints, including DFT SDC and timing analysis.
- Collaborate with RTL, physical design, and silicon validation teams to resolve integration issues.
- Support ATPG pattern generation, simulation, DRC analysis, and diagnosis.
- Mentor junior and mid-level DFT engineers on methodology and automation.
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