Lead RTL Engineer

Texas, United States. Bengaluru, Karnataka, India. Brazil. Mexico. Vietnam. ColombiaContractLead
Salary not disclosed
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Job Details

Experience
7+ years

Requirements

  • 7+ years of RTL design experience using SystemVerilog
  • Proven experience leading RTL development for processor, CPU, DSP, or datapath-intensive designs
  • Experience delivering at least one silicon tapeout through GDSII handoff
  • Strong synthesis and timing closure experience using industry-standard EDA tools
  • Deep understanding of microarchitecture and hardware design principles
  • Experience with advanced semiconductor process technologies (28nm or below preferred)
  • Ability to lead engineering teams while remaining highly hands-on technically
  • Strong communication and technical leadership skills

Responsibilities

  • Drive RTL implementation from architectural specification through tapeout
  • Lead RTL development for processor, CPU, DSP, or datapath-intensive designs
  • Perform RTL design and implementation
  • Execute synthesis and timing closure using EDA tools
  • Coordinate across architecture, verification, and physical design teams
  • Provide technical leadership to engineering teams while remaining hands-on
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