Lead RTL Engineer (CPU & Processor Design)
New
Based in IndiaFull-TimeLead
Salary not disclosed
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Job Details
- Experience
- 7+ years
Requirements
- 7+ years of RTL design experience using SystemVerilog in complex hardware environments
- Proven track record leading RTL development for CPU, DSP, or processor-class silicon projects
- At least one successful silicon tapeout experience, including GDSII handoff ownership
- Strong understanding of microarchitecture, datapath design, and computer architecture principles
- Experience with synthesis, timing closure, and EDA tool-based hardware validation workflows
- Exposure to advanced process nodes (28nm or below preferred)
- Ability to lead technical discussions while remaining deeply hands-on in RTL implementation
- Strong communication, problem-solving, and cross-functional collaboration skills
Responsibilities
- Designing, developing, and optimizing RTL in SystemVerilog for processor, DSP, and datapath-intensive architectures
- Driving microarchitecture implementation, synthesis, timing closure, and performance optimization across silicon blocks
- Collaborating closely with architecture, verification, and physical design teams to ensure seamless design integration
- Owning RTL delivery milestones through GDSII handoff and supporting successful silicon tapeout execution
- Providing technical leadership, guiding design decisions, and mentoring engineering contributors on best practices
- Ensuring design correctness, scalability, and compliance with advanced semiconductor process requirements
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