Senior FPGA Verification Engineer
U
Ursa MajorAerospace and Defense
RemoteFull-TimeSenior
Salary120,000 - 150,000 USD per year
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Job Details
- Experience
- 5+ years
- Required Skills
- Python
Requirements
- 5+ years’ experience with SystemVerilog Universal Verification Methodology (UVM), Pyuvm or similar verification methodology
- Experience with COCOTB and python-based HDL simulations
- Experienced in running ASIC/FPGA simulations using QuestaSim, VCS, Riviero-Pro, or Verilator
- Experienced in collecting ASIC/FPGA coverage metrics
- Experienced in defining test plans, generating test cases and testbench components
- Experienced in writing VHDL, Verilog or SystemVerilog code for ASIC/FPGA design
- Experience in Python scripting, simulations and tool development
Responsibilities
- Architect and generate ASIC/FPGA test benches
- Generate test cases and run simulations to verify the functionality of ASIC/FPGA code
- Generate and perform testing on target hardware as part of post-silicon validation or integrated test environment (Hardware in the Loop)
- Collect functional and code coverage metrics
- Validate and verify ASIC/FPGA requirements
- Help debug ASIC/FPGA design and/or test issues
- Prepare materials for peer reviews and major program design reviews
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