- Define and implement end-to-end DFT architecture for complex SoCs.
- Develop In-System Test (IST) and power-on self-test (POST) strategies.
- Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.
- Collaborate with Design, Physical Design, and Yield teams to ensure test coverage.
- Lead bring-up and debug phase on ATE to root-cause silicon failures.
- Optimize test time for high-performance AI accelerators.