- Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies.
- Create and execute coverage-driven verification plans aligned with design specifications.
- Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases.
- Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with RTL design engineers.
- Implement and track functional and code coverage, driving verification to closure.
- Develop reusable verification components and write SystemVerilog Assertions (SVA).
- Participate in design and verification reviews, providing input on design testability, correctness, and optimization.
- Automate regression testing and enhance verification infrastructure using Python and scripting.
- Contribute to continuous improvement of verification processes, tools, and methodologies.
Python