Senior Staff Digital Design Engineer
New
J
JobgetherSemiconductor Design
Remote-eligible position in the United StatesFull-TimeSenior
Salary$158,700–$238,100 USD
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Job Details
- Experience
- 12+ years of relevant experience; alternatively, 8+ years with a master’s degree or 5+ years with a PhD.
- Required Skills
- Python
Requirements
- Bachelor’s degree in Computer Engineering or a related technical discipline, with 12+ years of relevant experience; alternatively, 8+ years with a master’s degree or 5+ years with a PhD.
- 12+ years of hands-on RTL design experience, including at least 2–3 complete tapeout cycles, preferably involving mixed-signal or RF-integrated ICs.
- Strong expertise in digital logic design, micro-architecture, synthesis, timing closure, and semiconductor design methodologies.
- Advanced proficiency in Verilog and SystemVerilog for RTL development, behavioral modeling, and verification.
- Strong understanding of CDC analysis, clock gating, low-power design methodologies such as UPF/CPF, and static timing analysis.
- Experience with UVM-based verification, functional coverage, assertion-based verification, and DFT methodologies including scan, MBIST, and ATPG.
- Scripting experience with Python, Perl, UNIX shell, or similar tools for design automation and engineering productivity.
- Demonstrated ability to lead complex technical initiatives and mentor junior or mid-level engineers.
- Strong communication and collaboration skills.
Responsibilities
- Lead digital design for next-generation RAIN RFID reader ICs, taking ownership from architecture and micro-architecture through RTL implementation, tapeout, and post-silicon validation.
- Develop detailed micro-architectures, executable models, and RTL for complex digital and mixed-signal subsystems.
- Partner with chip architects and RF/analog engineers to define and implement advanced mixed-signal architectures, including control loops, calibration engines, and analog IP interfaces.
- Collaborate with verification and physical design teams to achieve robust functionality, timing closure, signal integrity, and production-ready silicon.
- Define and implement DFT strategies, including scan insertion, BIST, boundary scan, and related test methodologies for mixed-signal IC designs.
- Work with CAD/EDA engineering teams to improve ASIC/SoC design flows, methodologies, automation, and engineering best practices.
- Support post-silicon bring-up and debugging by correlating RTL and simulation results with laboratory measurements and silicon behavior.
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