Senior Staff RTL Verification Engineer
New
J
JobgetherSemiconductor Engineering
The position is remote-eligible in the United States, with Seattle also available as a work locationFull-TimeSenior
SalaryTypical U.S. base salary range of $158,700–$238,100
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Job Details
- Experience
- 12+ years of relevant experience; alternatively, 8+ years with a master's degree or 5+ years with a PhD
- Required Skills
- PythonRubyCI/CD
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline.
- 12+ years of professional experience in RTL verification, including tape-out and production.
- Strong experience verifying microcontroller microarchitectures and complex finite-state machines.
- Advanced proficiency in SystemVerilog and Universal Verification Methodology (UVM).
- Hands-on experience developing bus functional models, architectural checkers, and reusable verification infrastructure.
- Strong experience developing SystemVerilog assertions, coverage monitors, and functional coverage strategies.
- Experience defining verification metrics and using coverage analysis for tape-out readiness.
- Familiarity with CI/CD systems and RTL coverage tools.
- Scripting proficiency in Python, Perl, Ruby, or UNIX shell.
- Strong analytical and problem-solving skills for complex verification issues.
- Excellent written and verbal communication skills.
Responsibilities
- Drive RTL verification activities for next-generation RAIN RFID Reader ICs across the full product development lifecycle.
- Define and implement modern verification methodologies, infrastructure, and processes that improve design quality, coverage, and development efficiency.
- Develop SystemVerilog testbenches, bus functional models, subsystem behavioral models, architectural checkers, and reusable verification components.
- Create and execute both directed and constrained-random tests to validate complex functionality and achieve comprehensive functional coverage.
- Develop detailed verification plans and establish coverage metrics that provide confidence in design quality and tape-out readiness.
- Write SystemVerilog assertions, coverage monitors, and other automated checks to identify functional issues early.
- Develop CI/CD workflows, custom verification toolkits, and reporting solutions to improve verification productivity.
- Collaborate closely with digital logic, analog, test, and systems engineering teams.
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