Senior Staff Digital Design Engineer
New
I
ImpinjSemiconductors / IoT
Remote, USAFull-TimeSenior
Salary$158,700 - $238,100
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Job Details
- Experience
- 12 years of experience (or 8 years with MS or 5 years with a PhD)
- Required Skills
- Python
Requirements
- Bachelor’s degree in Computer Engineering.
- 12 years of experience (or 8 years with MS or 5 years with a PhD).
- 12+ years of RTL design experience.
- Experience with at least 2–3 full tapeout cycles, preferably on mixed-signal or RF-integrated ICs.
- Strong skills in digital logic design, micro-architecture definition, synthesis, and timing closure.
- Proficiency in Verilog and SystemVerilog for RTL development, behavioral modeling, and verification.
- Solid understanding of digital design methodologies including CDC analysis, clock gating, low-power design (UPF/CPF), and static timing analysis.
- Experience with UVM-based verification, functional coverage, assertion-based verification, and DFT implementation (scan, MBIST, ATPG).
- Scripting proficiency in Python, Perl, or UNIX shell for flow automation.
- Proven ability to lead technical workstreams and mentor junior engineers.
Responsibilities
- Drive the digital design of Impinj's next-generation RAIN RFID Reader ICs from architecture through tapeout and silicon validation.
- Develop micro-architectures, create executable models, and implement RTL for complex digital and mixed-signal IC subsystems.
- Collaborate with chip architects and RF/analog engineers to partition and realize advanced mixed-signal architectures.
- Partner with physical design and verification teams to ensure timing closure, signal integrity, and delivery of production-ready Reader ICs.
- Define and implement DFT strategies including scan insertion, BIST, and boundary scan.
- Work with CAD/EDA engineers to evolve ASIC/SoC design flows, methodologies, and best practices.
- Enhance existing RAIN RFID Reader products with new features, performance improvements, and power optimizations.
- Support post-silicon bring-up and debug by correlating RTL and simulation results with lab measurements.
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