Package Design Engineer

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SPD TechnologySemiconductor packaging
Mexico. Netherlands. Germany. France. United Kingdom. IsraelFull-TimeSenior
Salary not disclosed
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Job Details

Languages
English — Upper Intermediate or higher.
Experience
8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
Required Skills
Scripting

Requirements

  • Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
  • 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
  • Experience in chip package substrate layout, design verification, DFM, and taping out for production.
  • Experience in design automation and scripting.
  • English at Upper Intermediate level or higher.
  • Bonus: Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Bonus: Experience working with cross-functional chip design, SI/PI, and PCB design teams.
  • Bonus: Experience in 2.5D/3.5D advanced package design.
  • Bonus: Experience with physical verification flows, including LVS, DRC, and connectivity.
  • Bonus: Experience using CAD to create simple mechanical drawings, such as package outline drawings (POD).
  • Bonus: Ability to write scripts to customize Cadence or Mentor workflows.

Responsibilities

  • Develop physical package substrate designs for large-form-factor packages for ML high-performance computers.
  • Develop and implement methodology and CAD flows for efficient substrate design and improved productivity.
  • Manage chip-, package-, and system-level co-design initiatives and secure production sign-off for package designs.
  • Collaborate with SI/PI, thermal, and mechanical engineering teams to refine product package designs, test vehicles, and mock-up designs for product feasibility.
  • Define and document package substrate design requirements and the bill of materials (BOM).
  • Manage package design phases including routing feasibility studies, test vehicle development, product-level designs, design reviews, artwork export, DFM activities, and final manufacturing documentation.
  • Contribute to evaluation and adoption of advanced chip packaging technologies.
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