Senior Staff Engineer - Design Verification
J
JobgetherSemiconductor Engineering
Remote position available for candidates based in India.Full-TimeStaff
Salary not disclosed
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Job Details
- Experience
- 12+ years
- Required Skills
- Debugging
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related technical discipline.
- 12+ years of professional experience in design verification, with substantial exposure to complex SoC and IP verification.
- Proven experience defining and implementing verification architectures for high-speed interconnect protocols and sophisticated semiconductor designs.
- Strong hands-on expertise in SystemVerilog, UVM, coverage-driven verification, and SystemVerilog Assertions (SVA).
- Deep practical knowledge of PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, or comparable high-speed protocols.
- Strong understanding of SoC architecture, IP integration, high-speed interfaces, and verification methodologies.
- Demonstrated ability to lead complex debugging and problem-solving activities across simulation and hardware environments.
- Strong technical leadership skills, with the ability to influence engineering decisions.
- Excellent communication and mentoring capabilities, with a collaborative approach to working with cross-functional teams.
Responsibilities
- Define and execute scalable, comprehensive verification strategies and plans for high-speed PCIe, CXL, Ethernet, and related IP and SoC subsystems.
- Architect and develop reusable, layered UVM testbenches, verification environments, agents, and components for complex protocol verification.
- Apply deep protocol expertise to verify PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, and UCIe PHY and Adapter layers.
- Drive coverage-driven verification, including functional coverage, assertion-based verification, metrics analysis, and sign-off.
- Lead complex debug and root-cause analysis across simulation, emulation, prototyping, and silicon bring-up environments.
- Establish verification best practices, methodologies, and reusable frameworks to support multiple projects and tape-outs.
- Mentor junior and mid-level verification engineers, providing technical guidance and promoting strong verification discipline.
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