FPGA Digital Design Engineer
New
K
KeplerSatellite communications
Listing location: Toronto, Ontario / United States / Canada; Workplace type: RemoteFull-TimeMiddle
Salary not disclosed
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Job Details
- Experience
- 5+ yr. working experience with FPGA/RTL design
- Required Skills
- Python
Requirements
- Hold a Bachelor’s degree in Computer Engineering, Electrical Engineering, or equivalent.
- Have 5+ years of working experience with FPGA/RTL design.
- Have experience with Verilog, SystemVerilog, or VHDL, and be willing to learn or pivot to SystemVerilog.
- Have experience with Xilinx FPGAs, specifically Zynq and UltraScale.
- Understand timing principles, including clock domain crossing and timing closure.
- Have strong scripting skills, such as Python, Tcl, csh, or bash.
- Have experience with FPGA tools such as Vivado or Quartus and HDL simulation tools such as ModelSim.
- Preferred: Master of Science in Computer or Electrical Engineering, or equivalent.
- Preferred: Experience with coherent digital demodulation of waveforms such as BPSK, QPSK, or QAM.
- Preferred: Experience with memory-mapped interfaces such as AXI, Wishbone, or Avalon.
- Preferred: Experience with high-speed transceivers and protocols such as JESD204B, PCIe, or SATA.
- Preferred: Experience with linting tools, Questa Sim, or Riviera-Pro.
Responsibilities
- Develop custom IP for new features of Kepler satellite digital payloads.
- Iterate on current DSP and interface designs to improve reliability.
- Work with IP core vendors to integrate new functionality into Kepler designs.
- Work with lead engineers to develop communications and network architecture for the future satellite constellation.
- Participate in conceptual design studies of new spacecraft.
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