Senior Engineer - Silicon Physical Design (Italy based)

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Requirements:

• 10+ years of experience in Physical Design (RTL to GDS).
• Strong communication and teamwork skills.
• Expertise in synthesis, timing analysis, and timing closure.
• Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre).
• Proficiency in clocking techniques and CTS.
• Experience in IP integration across various domains.
• Strong scripting skills (Python, Tcl, or Perl).
• Proven problem-solving and debugging capabilities.
• Fluent in English (spoken and written).

Responsibilities:

• Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.
• Ensure timing closure, constraint generation, and optimization.
• Execute clock tree synthesis (CTS) and clock-building techniques.
• Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
• Utilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
• Develop automation scripts in Python, Tcl, or Perl.
• Debug and solve technical challenges related to physical design.
• Collaborate with architecture, RTL, and verification teams.