Sr RTL Design Engineer

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Requirements:

• Bachelor of Science degree in EE/ECE/CE/CS or related field required; MS or PhD highly desired.
• Knowledge of micro-processor architecture.
• Strong background in RTL design of power and area-efficient designs.
• Knowledge of logic design principles along with timing and power implications.
• Experience with Python and C/C++ programming.
• Experience with writing and debugging low-level firmware and kernels.
• Proficiency in RTL design and converging high-performance designs for performance, power, area, and frequency.

Responsibilities:

• Implement parameterized RTL designs using micro-architecture specifications.
• Conduct experiments with RTL and evaluate synthesis, timing, and power results.
• Enhance RTL design environment, tools, and infrastructure.
• Write, analyze and optimize low-level kernels for AI workloads using Tensix ISA features.
• Work with architects and other designers to improve the PPA (Performance, Power, Area) of designs.