CPU HW Engineer (CZ)

View full description

Requirements:

• Recent hands-on experience with IP/Processor development.
• Strong background in Digital Design, computer architecture, and embedded systems.
• Experience with ASIC, FPGA design, and IP verification (e.g., UVM).
• Preferred experience in AI, safety, and security.
• Experience in HLS using C++/Matlab/SystemC.
• Proficiency in VHDL/Verilog and SystemVerilog.
• SW skills in C/C++, Assembly, HLS, and scripting languages (bash, Python).
• Fluency in written and spoken English; Czech is an advantage.
• Excellent communication skills and a pragmatic, proactive approach.

Responsibilities:

• Innovate, develop, integrate, and evaluate (micro-)architectural IP cores in Codasip Studio for RISC-V architecture.
• Customize and enhance existing Codasip RISC-V IP cores to meet partners' and customers' requirements.
• Participate in design verification and FPGA-based demonstrators.
• Contribute to joint proof-of-concept demos with academic and industrial partners.
• Report technical results at international venues like the RISC-V summit.