Staff Engineer, SoC Design Verification

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Requirements:

• 10+ years experience in developing software solutions in C/C++
• Expert level knowledge in HVL methodology (UVM)
• Solid verification skills in constrained random testing
• Strong programming skills in C++ and Assembly
• Knowledge in storage interfaces like PCIe and DRAM

Responsibilities:

• Understand system and micro-architecture
• Create verification plan and requirements
• Generate random test cases
• Create coverage model for function coverage
• Build auto verification flows