Senior Design Verification Engineer
New
Fully remote work model within IndiaFull-TimeSenior
Salary not disclosed
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Job Details
- Experience
- 8–12 years
- Required Skills
- PythonC++
Requirements
- 8–12 years of experience in design verification
- Expertise in interconnect protocols: AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe
- Deep knowledge of UVM, SystemVerilog, and SVA
- Coverage-driven verification methodologies
- Programming in SystemVerilog, C/C++, and Python
- Understanding of cache coherency and memory consistency models
- Experience with AI-assisted development workflows
- Formal verification, emulation, or FPGA-based validation experience is a plus
- Knowledge of system-level IPs like MMUs, interrupt controllers, or power/debug features
Responsibilities
- Lead end-to-end verification of IP and subsystem-level designs
- Own verification planning, test development, and coverage closure
- Build and maintain scalable verification environments using UVM and SystemVerilog
- Develop reusable testbenches, checkers, and automation frameworks
- Collaborate with architecture, design, and software teams
- Drive root-cause analysis of simulation failures
- Execute functional coverage planning
- Participate in simulation and formal verification
- Mentor junior engineers
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